Integrated circuits (ICs) generally include various modules combined to perform various functions. For example, a digital signal processor (DSP) includes processor and memory blocks embedded in the IC. The memory blocks containing plurality of addressable memory locations are tested for defects, ensuring the operability of the IC. To test these blocks, special test circuits, referred to as “Built-In Self Test” (BIST) circuits are incorporated into the IC. BIST circuits generate a test pattern to determine whether the memory block is defective or not. In some cases, if the number of defective memory locations is relatively low, the BIST circuit provides redundant rows and/or columns that are used to repair defective rows and columns in the memory block.
The embedded memory blocks are susceptible to manufacturing variations and hence more defects. All the memory blocks are tested serially by BIST circuits. A single BIST circuit performing testing and repairing of memory blocks takes longer time especially when density of memory blocks on the IC is high. One solution would be to get more BIST circuits on the chip, but this is not practical as it results in increased area and hence higher costs.
Thus, there is a need to efficiently test on chip memories without requiring an enormous amount of time and also without increasing overall area of IC.